1. Field of the Invention
The present invention relates to a clock signal producing device utilized for a video apparatus such as a video tape recorder.
2. Description of the Related Art
FIG. 1 is a block diagram of a clock signal producing device of the prior art as an example of its configuration. The clock signal producing device comprises a phase comparator 101, a loop filter 102, a voltage controlled oscillator (referred to as VCO) 103 and a 1/4 frequency divider 104. A clock signal S.sub.CL outputted from the VCO 103 is divided into 1/4 by the 1/4 frequency divider 104. The phase comparator 101 compares a clock signal S.sub.CL divided into 1/4 with a reference signal S.sub.REF in a phase. An output signal from the phase comparator 101, that is, a phase error signal is supplied to the loop filter (low pas filter) 102. The loop filter 102 eliminates high frequency components of the phase error signal. An output signal from the loop filter 102 is supplied to a control terminal of the VCO 103. Accordingly the VCO 103 outputs the clock signal S.sub.CL of a frequency in response to an output of the loop filter 102 which is supplied to the control terminal of the VCO 103. According to this configuration, a clock signal S.sub.CL is obtained, wherein a frequency of the clock signal S.sub.CL is 4 times higher than that of a reference signal S.sub.REF and a phase of the clock signal S.sub.CL is locked with that of the reference signal S.sub.REF. For example, in a video tape recorder (referred to as VTR), it is conceivable that a signal having a frequency f.sub.SC of a color sub-carrier is employed as a reference signal S.sub.REF so as to obtain a clock signal S.sub.CL of a frequency of 4}.times.f.sub.SC.
A delay device having a delay time of 1 H (one horizontal scanning period) is necessary for processing a vertical synchronizing signal of video signals in a VTR. In case that a circuit is designed for coping with various broadcasting systems such as NTSC and PAL, it is necessary to prepare a wide variety of delay stages (i.e. 1 H/clock period) of a delay device in response to the various broadcasting systems if a clock frequency f.sub.CL of the delay device is set to an integer multiple of a color sub-carrier frequency f.sub.SC. In addition thereto, a configuration of the circuit becomes more complicated. For example, a number of delay stages of a 1 H delay device is 1135 stages for the PAL while 910 stages for the NTSC, in case that a clock frequency is set to 4 times the color sub-carrier frequency f.sub.SC, that is, 4.times.f.sub.SC.
With respect to a frequency of a reference signal as a clock signal of a digital signal processing circuit, a digital VTR complying with the DV (Digital Video) Standard or the DVC (Digital Video Cassette) Standard employs a frequency such as 13.5 MHz, which is not an integer multiple of a color sub-carrier frequency f.sub.SC for any broadcasting systems. It is difficult to produce a clock signal of a frequency, which is not an integer multiple of a color sub-carrier frequency f.sub.SC, from a reference signal of a frequency f.sub.SC inputted to the phase comparator 101 by the conventional circuit as shown in FIG. 1.